The present invention relates to a semiconductor device, and particularly to a technique effectively applied to a semiconductor antenna switch mounted onto radio communication equipment, for example.
Japanese Unexamined Patent Publication No. 2008-11320 (patent document 1) has described a configuration in which the gate widths of some field effect transistors in a plurality of stages of field effect transistors coupled in series are set narrower than those of other field effect transistors, and capacitors having fixed capacitances are respectively coupled between the gates and drains of the field effect transistors set narrow in gate width and between the gates and sources thereof.